Planned for Next Quarter</u></b><u><p>
</u>
*Implement optical cavities to optimize SiGe/Si HIP detectors, and characterize
performance.  (JPL)<p>

*Fabricate "AIRS type" InGaAs/GaAs QWIP linear array.  (JPL)<p>

*Demonstrate PV detector operation in As-rich InAsSb superlattice material,
with cutoff wavelength &gt; 12 um.  (JPL)<p>

*Deliver TES PC arrays of HgZnTe to JPL; demonstrate long-wave HgZnTe PV
devices.  (LaRC)<u><p>
</u>
*Complete fabrication of "insurance lot" of 1 x 32 low-temperature readouts at
Hughes Technology Center.  Complete characterization of 1st lot; initiate
low-temperature testing of "insurance lot".  (ARC)<p>

*Determine noise and pixel operability of low-background performance of the
(second) 256 x 256 Si:As IBC array.  (ARC)<u><p>


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